A modern application specific integrated circuit (ASIC) must meet very stringent design and performance specifications. One example of an ASIC is a circuit element referred to as a serializer/deserializer (SERDES). As its name implies, a SERDES converts a parallel bit stream to a high speed serial bit stream, transmits it across a channel, then the serial bit stream is converted back to a parallel bit stream. A typical SERDES is organized into blocks of transmitters and receivers having digital to analog conversion (DAC) functionality and analog to digital conversion (ADC) functionality. Normally, the receivers and transmitters operate on differential signals. Differential signals are those that are represented by two complementary signals on different conductors, with the term “differential” representing the difference between the two complementary signals. All differential signals also have what is referred to as a “common mode,” which represents the average of the two differential signals.
In a SERDES receiver, it is desirable to observe one or more voltages within the receiver architecture. One of the voltages sought to be observed is the receiver's common mode voltage. Unfortunately, observing voltages inside of a SERDES receiver is difficult because of the limited availability of pins through which to observe the desired signals.
FIG. 1 is a schematic diagram illustrating an existing digital to analog converter (DAC) that may be part of a SERDES receiver, configured to perform common mode tracking on a differential input signal. The DAC 1 comprises a first DAC 2 and a second DAC 4. For example purposes only, the first DAC 2 receives digital input signals on connection 6. The digital input signal on connection 6 typically comprises a multi-bit wide (parallel) stream and can be referred to as the positive (p) or true (T), component of a differential input signal. The second DAC 4 receives digital input signals on connection 7. The digital input signal on connection 7 typically comprises a multi-bit wide (parallel) stream and can be referred to as the negative (n) or complement (C) component of a differential input signal. During normal operation, the differential signals are always complementary so that together they output a differential signal, centered around the common mode that the rest of the circuit tracks. The output of the DAC 2 on connection 11 is a single value analog version of the digital input signal on connection 6, and the output of the DAC 4 on connection 12 is a single value analog version of the digital input signal on connection 7.
The signal on connection 11 is provided to a resistor 8 and the signal on connection 12 is provided to a resistor 9. The resistors 8 and 9 respectively illustrate the output impedance of the DAC 2 and the DAC 4. A supply voltage Vcc is provided to resistor 14 to generate the positive output signal “outp” on connection 17. The supply voltage Vcc is provided to resistor 16 to generate the negative output signal “outn” on connection 18. The output signal, outp, on connection 17 is generated by a current 19 flowing through a current source 23 and the output signal, outn, on connection 18 is generated by a current flowing in connection 21 through a current source 24.
A common mode DAC output signal referred to as “Vcm_out” is provided to an operational amplifier 30 on connection 35. A SERDES receiver's filtered common mode signal, referred to as “vsumdc” is provided to the operational amplifier 30 on connection 41. The common mode DAC output signal Vcm_out is generated by taking the outp signal on connection 17 and the outn signal on connection 18 and combining them through respective resistors 32 and 34 to generate the common mode DAC output signal connection 35. Similarly, the receiver's common mode signal, vsumdc, on connection 41 is generated by taking the differential receiver inputs vsum1 (or RXin1) and vsum2 (or RXin2) on connections 36 and 37, and processing them through respective resistors 38 and 39, to develop the receiver's filtered common mode signal on connection 41. The output of the operational amplifier 30 is controlled by the difference between Vcm_out and vsumdc, and tends to drive the nodes outp 17 and outn 18 toward the value of vsumdc. The resistors 8 and 9, the resistors 14 and 16, and the current sources 19 and 21 allow the outp and outn signals to have an adjustable common mode, that can track the vsum1, vsum2 common mode, vsumdc. The resistor network also allows the DAC output to be attenuated, so that it has a range that is closer to the range expected at vsum1 and vsum2
FIG. 2 is a schematic diagram illustrating the DAC of FIG. 1 in additional detail. Elements in FIG. 2 that are identical to corresponding elements in FIG. 1 are identically numbered. The DAC 51 illustrates the operational amplifier 30 of FIG. 1 in additional detail. The operational amplifier 30 comprises a first stage having transistors 52 and 54, a second stage having transistors 61, 62, 66 and 67, and current sources 58 and 59 arranged in what is referred to as a folded cascode architecture.
The Vcm_out signal on connection 35 is provided to the gate of transistor 52 and the vsumdc signal on connection 41 is provided to the gate of transistor 54. When conducting, the transistors 52 and 54 steer a current generated by the current source 55. The drain 56 of the transistor 52 is coupled to the source of transistor 61. The drain 57 of the transistor 54 is coupled to the source of transistor 62. The gates of transistors 61 and 62 are biased by a bias voltage signal Vg on connection 64. The transistor 66 is configured as a diode. Depending on the values of Vcm_out and vsumdc, current flows through the current sources 58 and 59, creating the above-mentioned output on connection 31. The output of the operational amplifier 30 on connection 31 is provided to a resistor 69 and a capacitor 72, which form a high impedance dominant pole at node 71. The resistor 69 and capacitor 72 need not necessarily be separate components in the circuit, and are shown to illustrate that the output of the operational amplifier 30 is at a high impedance, and the gates of the transistors 74 and 75 have a large capacitance. Therefore, the high impedance at node 71 acts like a large resistive/capacitive (RC) circuit, which stabilizes the loop.
The current source shown graphically in FIG. 1 using reference numeral 23 is represented by an n-type metal oxide semiconductor (NMOS) transistor 74. The current source shown graphically in FIG. 1 using reference numeral 24 is represented by an NMOS transistor 75. The positive output outp is shown on connection 17, and the negative output outn is shown on connection 18.
Accordingly, the DAC 51 that exists in a SERDES receiver currently has access to the incoming receiver differential signals. Therefore, what is needed is a way of using the information provided by the operational amplifier 30 to measure the DAC common mode voltage.